1. Field of the Invention
The present invention relates generally to a refreshing method for a memory device, and more particularly, to a refreshing method for a memory device which can reduce leakage current and noise.
2. Description of Related Art
DRAM is a type of memory that is being most widely used. The DRAM stores data using capacitors and, because charges in the capacitors gradually disappear, additional periodic refreshing operations are required. FIG. 1 illustrates a structure of a basic unit of a conventional DRAM. FIG. 2 illustrates a timing diagram of various signals of FIG. 1. Referring to FIGS. 1 and 2, during an equalization period T21, because the level of signals EQL11, EQL12, MUX11 and MUX12 is maintained at a voltage VINT2, bit lines (BL11, /BL12, BL12 and /BL12) and sense lines (BLM11 and BLM12) are electrically coupled to each other and have a potential equal to a reference voltage VEQL2 wherein the level of the reference voltage VEQL12 is set as a half of a highest level of the bit line VBLH2.
Afterwards, in order to refresh a memory cell 131 coupled to a word line WLR0, a memory cell array 130 is enabled during a refreshing period T22. At this time, the level of the signals EQL12 and MUX11 is switched to a voltage VSS2, such that the bit lines BL12 and /BL12 are not conducted to each other, and a sense amplifier 120 and a memory cell array 110 are not electrically coupled to each other. Next, the word line WLR0 is used to address the memory cell to be accessed. During a signal generating stage, the memory cell 131 is turned on and the signals to be read are generated on the bit lines BL12, /BL12 and the sense lines BLM11, BLM12. At this time, the sense amplifier 120 amplifies the signals on the sense lines BLM11, BLM12, thereby refreshing the memory cell 131.
It should be noted that continuously reducing of the DRAM core structure size would cause the problem of leakage current between the bit lines to be more and more serious. This is mainly because, during the equalization period, a parasitic capacitor in the memory cell forms an undesired conducting path such that a leakage current, for example, as indicated by I11 in FIG. 1, is generated between the bit lines. This problem can be mitigated by adding a current limiter. However, the leakage current arising from the sense amplifier 120, for example, as indicated by I12 in FIG. 1, cannot be suppressed.
In order to prevent the leakage current arising from the sense amplifier 120, as shown in FIG. 3, at an initial stage of the refreshing period T22, the signals MUX11 and MUX12 are conventionally switched to the voltage VSS2 at the same time. At this time, the sense lines BLM11 and BLM12 are maintained in a floating state, thereby reducing the possibility of generating the leakage current. However, when the sense lines BLM11 and BLM12 are maintained in the floating state at the same time, noise may be generated which would affect a noise margin of the entire system.